We are seeking a Senior Engineer – High-Speed Signal Integrity to drive research in next-generation high-speed wireline electrical communication. This role is part of the High-Speed High-Frequency team within the Board Engineering department (Lab) at our Grenoble Research Center.

You will work closely with our HQ technical team in China to develop cutting-edge high-speed SerDes systems (112 Gbit/s and beyond). You will contribute to the design, simulation, and analysis of high-speed interconnects and PCBs while shaping the technology roadmap for high-speed signal integrity.

📍 Location: Grenoble Research Center

💰 Salary: €80,000 - €130,000 per annum (DOE)
🕒 Start Date: ASAP

About the GrenoblAbout the Rolee Research Center

Founded in 2019 by the Hardware Engineering Institute of 2012 Laboratories, our Grenoble Research Center is home to 30+ engineers, including PhDs, technical experts, and scholars from world-renowned institutions. Our young and dynamic team is dedicated to solving complex challenges in high-speed technologies for the ICT industry.

As we expand our high-speed research team, we offer a unique opportunity to work on state-of-the-art technologies with a global impact.

Duties and Responsibilities

🔹 Research and develop high-speed interconnects (passive channels) for next-gen systems 112+Gbps per lane
🔹 High-speed PCB design, simulation, and signal integrity analysis
🔹 Conduct lab verification of high-speed designs
🔹 Collaborate with the HQ team in China through technical reviews, reporting, and project planning
🔹 Define the technology roadmap and research strategy for high-speed interconnects

Requirements

✅ Master’s degree or PhD preferred in Electrical Engineering, Information Technology, Communication Engineering, or Electromagnetic Science
✅ Extensive experience in high-speed telecom/communication hardware architecture design
✅ Proven track record in 56Gbps+ product development and delivery
✅ Deep expertise in high-frequency PCB design, including impedance control and crosstalk management
✅ Experience in system-level simulation (PCB, connector, and cable-level analog signal simulation)
✅ Strong understanding of PCB/HDI stack-up design, fabrication limitations, and cost factors
✅ Knowledge of high-speed SerDes architectures (Rx/Tx SerDes PHY, equalization techniques, CDR, DSP challenges)

Preferred Skills

➕ Familiarity with high-speed serial hardware (SerDes, ASIC, DSP, PCB, connectors)
➕ Hands-on expertise in high-speed lab experiments (real-time oscilloscopes, VNAs) and simulation correlation
➕ Knowledge of industry standards (IEEE 802.3, OIF-CEI, InfiniBand, CEI-224G)
➕ Active participation in conferences and industry events
➕ Passion for technology and innovation, with a strong drive to contribute to high-speed signal integrity research

Technical Tools & Work

🔧 High-Speed / High-Frequency Design & Simulation: CST, ANSYS HFSS
🔧 SI Analysis: ADS, Sigrity, MATLAB, Python
🔧 SerDes Modeling & Simulation: Python (preferred), MATLAB, Verilog-A, ADS

Benefits

🚀 Work on cutting-edge 112 Gbit/s+ SerDes systems
🌍 Collaborate with a global R&D team
🎓 Engage in high-impact research with industry experts
📈 Shape the future of high-speed signal integrity

👉 Apply now to be part of a world-class research team in high-speed communication!

How to Apply

Please submit your resume and a cover letter detailing your experience and suitability for the role. We look forward to exploring how you can contribute to our team’s innovative projects in high-speed interconnection and board-level process reliability.

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